The present invention relates to a metal-oxide semiconductor (MOS), broadly a metal-insulated semiconductor (MIS) dynamic semiconductor memory device having stacked-capacitor type memory cells.
Recently, MOS memory cells of a one-transistor one-capacitor type have come into use in MOS dynamic memory devices. Fine lithographic technology has been developed so as to reduce the size of the elements of each memory cell, thereby obtaining a large capacity of a highly integrated semiconductor device. However, there is a limit to obtaining a high integration and a large capacity by size reduction only. In addition, size reduction of memory cells increases the generation rate of soft errors and the number of harmful effects due to hot electrons and hot holes.
For improving memory cells of a one-transistor one-capacitor type, stacked-capacitor type memory cells have been proposed (see: Technical Digest of the Institute of Electronics and Communication Engineers of Japan, SSD80-30, 1980, July). Each stacked-capacitor type memory cell includes a transfer transistor, which is the same as that of the conventional memory cell, and a capacitor, which comprises an electrode extending over a thick field-insulating layer, a counter electrode over its own transfer transistor, and an insulating layer therebetween, thereby increasing the capacitance of the capacitor.
Japan Unexamined patent publication (Kokai) No. 55-154762, published on Dec. 2, 1980, discloses a semiconductor memory device having stacked-capacitor type memory cells each of which includes a capacitor, formed by a dielectric layer and two opposing conductive layers on the surfaces thereof placed above a transistor region for increasing the capacitance of the capacitor while maintaining the high integration.
In the prior art, however, there are disadvantages of a low integration, lack of reliability, etc. These disadvantages will be discussed later with reference to a specific example.